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8-bit programmable 2- to 3-phase synchronous buck controller ADP3193 features selectable 2- or 3-phase operation at up to 1 mhz per phase 7.7 mv worst-case differential sensing error over temperature logic-level pwm outputs for interface to external high power drivers enhanced pwm flex mode for excellent load transient performance active current balancing between all output phases built-in power-good/crowbar bl anking supports on-the-fly vid code changes digitally programmable 0.5 v to 1.6 v output supports both vr10.x and vr11 specifications programmable short-circuit protection with programmable latch-off delay applications desktop pc power supplies for next generation intel? processors vrm modules general description the ADP3193 1 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 v main supply into the core supply voltage required by high per- formance intel processors. it uses an internal 8-bit dac to read a voltage identification (vid) code directly from the processor, which is used to set the output voltage between 0.5 v and 1.6 v. this device uses a multimode pwm architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for vr size and efficiency. the phase relation- ship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. the ADP3193 also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. the ADP3193 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power- good output that accommodates on-the-fly output voltage changes requested by the cpu. 1 protected by u.s. patent number 6,683,441; other patents pending. functional block diagram shunt regulator vc dac dac + 150mv 850mv dac ? 350mv csref 2/3-phase driver logic enset 14 1 2 8 7 16 5 3 32 ? + ? + ? + uvlo shutdown 15 22 21 20 19 18 17 13 11 12 4 6 boot voltage and soft start control delay reset reset reset vid7 24 vid6 25 vid5 26 vid4 27 vid3 28 vid2 29 vid1 30 vid0 31 ADP3193 + ? cmp + ? cmp + ? cmp crowbar current limit current measurement and limit precision reference 23 9 10 + ? + ? ? + gnd en delay ilimit pwrgd comp fbrtn vidsel iref pwm2 pwm3 sw3 sw2 sw1 csref cscomp cssum fb pwm1 ss od v cc r a mpadj rt current balancing circuit oscillator 06263-001 figure 1. the ADP3193 has a built-in shunt regulator that allows the part to be connected to the 12 v system supply through a series resistor. the ADP3193 is specified over the extended commercial temperature range of 0c to 85c and is available in a 32-lead lfcsp. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
ADP3193 rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 test circ u its ....................................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ........................................................................ 9 start-up sequence ........................................................................ 9 phase detection sequence ........................................................... 9 master clock frequency ............................................................ 10 output voltage differential sensing ........................................ 10 output current sensing ............................................................ 10 current control mode and thermal balance ........................ 10 volt age c ont rol mo de ................................................................ 10 current reference ...................................................................... 11 enhanced pwm mode .............................................................. 11 delay timer ................................................................................. 11 soft start ...................................................................................... 11 current-limit, short-circuit, and latch-off protection ...... 11 dynamic vid ............................................................................. 12 power-good monitoring ........................................................... 12 output crowbar ......................................................................... 12 output enable and uvlo ........................................................ 13 application information ................................................................ 19 setting the clock frequency ..................................................... 19 soft start delay time ................................................................. 19 current-limit latch-off delay times .................................... 19 inductor selection ...................................................................... 19 current sense amplifier ............................................................ 20 inductor dcr temperature correction ................................. 21 output offset .............................................................................. 21 c out selection ............................................................................. 21 power mosfets ......................................................................... 22 ramp resistor selection ............................................................ 24 comp pin ramp ....................................................................... 24 current-limit setpoint .............................................................. 24 feedback loop compensation design .................................... 24 c in selection and input current di/dt reduction .................. 26 shunt resistor design ................................................................ 26 tuning the ADP3193 ................................................................. 27 layout and component placement ......................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 8/06revision a: initial version
ADP3193 rev. a | page 3 of 32 specifications vcc = 5 v, fbrtn = gnd, t a = 0c to 85c, unless otherwise noted. 1 table 1. parameter symbol conditions min typ max unit reference current reference bias voltage v iref 1.5 v reference bias current i iref r iref = 100 k 14.25 15 15.75 a error amplifier output voltage range 2 v comp 0 4.4 v accuracy v fb relative to nominal dac output, referenced to fbrtn (see figure 2 ) ?7.7 +7.7 mv v fb(boot) in startup 1.092 1.1 1.108 v differential nonlinearity ?1 +1 lsb input bias current i fb i fb = i iref 13.5 15 16.5 a fbrtn current i fbrtn 65 200 a output current i comp fb forced to v out C 3% 500 a gain bandwidth product gbw (err) comp = fb 20 mhz slew rate comp = fb 25 v/s boot voltage hold time t boot c delay = 10 nf 2 ms vid inputs input low voltage v il(vid) vid(x), vidsel 0.4 v input high voltage v ih(vid) vid(x), vidsel 0.8 v input current i in(vid) ?1 a vid transition delay time 2 vid code change to fb change 400 ns no cpu detection turn-off delay time 2 vid code change to pwm going low 5 s oscillator frequency range 2 f osc 0.25 4 mhz frequency variation f phase t a = 25c, r t = 210 k, 3-phase 240 260 293 khz t a = 25c, r t = 100 k, 3-phase 530 khz t a = 25c, r t = 40 k, 3-phase 1000 khz output voltage v rt r t = 243 k to gnd 1.9 2.0 2.1 v rampadj output voltage v rampadj rampadj C fb ?50 +50 mv rampadj input current range i rampadj 1 50 a current sense amplifier offset voltage v os(csa) cssum C csref (see figure 2 ) ?1.0 +1.0 mv input bias current i bias(cssum) ?10 +10 na gain bandwidth product gbw (csa) cssum = cscomp 10 mhz slew rate c cscomp = 10 pf 10 v/s input common-mode range cssum and csref 0 3.5 v output voltage range 0.05 3.5 v output current i cscomp 500 a current limit latch-off delay time t oc(delay) c delay = 10 nf 8 ms current balance amplifier common-mode range v sw(x)cm ?600 +200 mv input resistance r sw(x) sw(x) = 0 v 10 17 26 k input current i sw(x) sw(x) = 0 v 8 12 20 a input current matching i sw(x) sw(x) = 0 v ?4 +4 % current limit comparator ilimit bias current i ilimit i ilimit = 2/3 i iref 9 10 11 a ilimit voltage v ilimit r ilimit = 121 k (v ilimit = (i ilimit r ilimit )) 1.09 1.21 1.33 v maximum output voltage 3 v current-limit threshold voltage v cl v csref ? v cscomp , r ilimit = 121 k 80 100 125 mv current-limit setting ratio v cl /v ilimit 82.6 mv/v
ADP3193 rev. a | page 4 of 32 parameter symbol conditions min typ max unit delay timer normal mode output current i delay i delay = i iref 12 15 18 a output current in current limit i delay(cl) i delay(cl) = 0.25 i iref 3.0 3.75 4.5 a threshold voltage v delay(th) 1.6 1.7 1.8 v soft start output current i ss during startup, i ss = i iref 12 15 18 a enable input threshold voltage v th(en) 800 850 900 mv hysteresis v hys(en) 80 100 125 mv input current i in(en) ?1 a delay time t delay(en) en > 950 mv, c delay = 10 nf 2 ms od output output low voltage v ol( od ) 160 500 mv output high voltage v oh( od ) 4 5 v power good comparator undervoltage threshold v pwrgd(uv) relative to nominal dac output ?400 ?350 ?300 mv overvoltage threshold v pwrgd(ov) relative to nominal dac output 100 150 200 mv output low voltage v ol(pwrgd) i pwrgd(sink) = -4 ma 150 300 mv power good delay time during soft start 2 c delay = 10 nf 2 ms vid code changing 100 250 s vid code static 200 ns crowbar trip point v crowbar relative to nominal dac output 100 150 200 mv crowbar reset point relative to fbrtn 320 375 430 mv crowbar delay time t crowbar overvoltage to pwm going low vid code changing 100 250 s vid code static 400 ns pwm outputs output low voltage v ol(pwm) i pwm(sink) = ?400 a 160 500 mv output high voltage v oh(pwm) i pwm(source) = 400 a 4.0 5 v supply v system = 12 v, r shunt = 340 (see figure 2 ) vcc 2 vcc 4.65 5 5.55 v dc supply current i vcc v system = 13.2 v, r shunt = 340 25 ma uvlo turn-on current 6.5 11 ma uvlo threshold voltage v uvlo vcc rising 9 v uvlo turn-off voltage vcc falling 4.1 v 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not tested in production.
ADP3193 rev. a | page 5 of 32 test circuits 1.25v 8-bit code 1k? 1 32 1f 100nf 100nf 20k ? 10nf 10nf 100k? 12v 680 ? 680? + 250k ? 06263-002 vid7 vcc pwm1 pwm2 pwm3 sw1 sw2 sw3 vidsel vid0 vid1 vid2 vid3 vid4 vid5 vid6 rt rampadj csref cssum cscomp gnd od iref en pwrgd fbrtn fb comp ss delay ilimit ADP3193 figure 2. closed-loop ou tput voltage accuracy cssum 13 cscomp 12 23 vcc csref 11 gnd 14 39k ? 680 ? 680 ? 100nf 1k? 1v ADP3193 v os = cscomp ? 1v 40 12v 0 6263-003 figure 3. current sense amplifier v os 23 vcc 10k ? 1v ADP3193 680 ? 680 ? 12v + 5 comp 4 fb 11 csref 14 gnd vid dac 06263-004 figure 4. positioning voltage
ADP3193 rev. a | page 6 of 32 absolute maximum ratings table 2. parameter rating vcc ?0.3 v to +6 v fbrtn ?0.3 v to +0.3 v pwm1 to pwm3, rampadj ?0.3 v to vcc + 0.3 v sw1 to sw3 ?5 v to +25 v <200 ns ?10 v to +25 v all other inputs and outputs ?0.3 v to vcc + 0.3 v storage temperature range ?65c to +150c operating ambient temperature range 0c to 85c operating junction temperature 125c thermal impedance ( ja ) 32.6c/w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages referenced to gnd. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ADP3193 rev. a | page 7 of 32 pin configuration and fu nction descriptions pin 1 indicator 1 en 2 pwrgd 3 fbrtn 4 fb 5 comp 6 ss 7 delay 8 ilimit 24 vid7 23 vcc 22 pwm1 21 pwm2 20 pwm3 19 sw1 18 sw2 17 sw3 9 r t 1 0 r a m p a d j 1 1 c s r e f 1 2 c s s u m 1 3 c s c o m p 1 4 g n d 1 5 o d 1 6 i r e f 3 2 v i d s e l 3 1 v i d 0 3 0 v i d 1 2 9 v i d 2 2 8 v i d 3 2 7 v i d 4 2 6 v i d 5 2 5 v i d 6 ADP3193 top view (not to scale) 06263-005 notes 1. the exposed epad on bottom side of package is an electrical connection and should be soldered to ground. figure 5. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 en power supply enable input. pulling this pin to gnd disables the pwm outputs and pulls the pwrgd output low. 2 pwrgd power-good output. open-drain output that signals when the output voltage is outside of the proper operating range. 3 fbrtn feedback return. vid dac and error amplifier re ference for remote sensing of the output voltage. 4 fb feedback input. error amplifier input for remote sensing of the output voltage. an external resistor between this pin and the output voltage sets the no load offset point. 5 comp error amplifier output and compensation point. 6 ss soft start delay setting input. an external capacitor co nnected between this pin and gnd sets the soft start ramp-up time. 7 delay delay timer setting input. an exte rnal capacitor connected between this pin and gnd sets the overcurrent latch-off dela y time, boot voltage hold time, en delay time, and pwrgd delay time. 8 ilimit current-limit set point. an extern al resistor from this pin to gnd sets the current-limit threshold of the converter. 9 rt frequency setting resistor input. an external resistor co nnected between this pin and gnd sets the oscillator frequency of the device. 10 rampadj pwm ramp current input. an external resistor from the converter input voltage to this pin sets the internal pwm ramp . 11 csref current sense reference voltage input. the voltage on this pin is used as the reference for the current sense amplifie r and the power-good and crowbar functions. this pin should be connected to the common point of the output inductors. 12 cssum current sense summing node. external resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. 13 cscomp current sense compensation point. a resistor and capacitor from this pin to cssum determines the gain of the current sense amplifier and the positioning loop response time. 14 gnd ground. all internal biasing and the logic output signals of the device are referenced to this ground. 15 od output disable logic output. this pin is actively pulled low when the en input is low or when vcc is below its uvlo threshold to signal to the driver ic that the driv er high-side and low-side outputs should go low. 16 iref current reference input. an external resistor from this pin to ground sets the reference current for i fb , i delay , i ss , and i ilimit . 17 to 19 sw3 to sw1 current balance inputs. inputs for measuring the current level in each phase. the sw pins of unused phases should be left open. 20 to 22 pwm3 to pwm1 logic-level pwm outputs. each output is connected to the in put of an external mosfet dr iver, such as the adp3120a. connecting pwm3 output to vcc causes that phase to turn off, allowing the ADP3193 to operate as a 2- or 3-phase controller. 23 vcc supply voltage. a 340 resistor should be placed betwee n the 12 v system supply and the vcc pin. the internal shunt regulator maintains vcc = 5 v. 24 to 31 vid7 to vid0 voltage identification dac inputs. these eight pins are pulled down to gnd, providing a logic zero if left open. when in normal operation mode, the dac output programs the fb regulation voltage from 0.5 v to 1.6 v (see table 4 ). 32 vidsel vid dac selection pin. the logic state of this pin dete rmines whether the internal vid dac decodes vid0 to vid7 as extended vr10 or vr11 inputs.
ADP3193 rev. a | page 8 of 32 typical performance characteristics 6000 0 13 06263-017 rt (k ? ) frequency (khz) 5000 4000 3000 2000 1000 27 39 50 68 82 130 210 248 270 430 742 850 master clock figure 6. master cl ock frequency vs. rt
ADP3193 rev. a | page 9 of 32 theory of operation the ADP3193 combines a multimode, fixed frequency, pwm control with multiphase logic outputs for use in 2- and 3-phase synchronous buck cpu core supply power converters. the internal vid dac is designed to interface with the intel 8-bit vrd/vrm 11 and 7-bit vrd/vrm 10 cpus. multiphase operation is important for producing the high currents and low voltages demanded by todays microprocessors. handling the high currents in a single-phase converter places high thermal demands on the components in the system, such as the inductors and mosfets. the multimode control of the ADP3193 ensures a stable, high performance topology for the following: ? balancing currents and thermals between phases ? high speed response at the lowest possible switching frequency and output decoupling ? minimizing thermal switching losses by using lower frequency operation ? tight load line regulation and accuracy ? high current output due to 3-phase operation ? reduced output ripple due to multiphase cancellation ? pc board layout noise immunity ? ease of use and design due to independent component selection ? flexibility in operation for tailoring design to low cost or high performance start-up sequence the ADP3193 follows the vr11 start-up sequence shown in figure 7 . after both the en and uvlo conditions are met, the delay pin goes through one cycle (td1). the first three clock cycles of td2 are blanked from the pwm outputs and used for phase detection as explained in the phase detection sequence section. then, the soft start ramp is enabled (td2), and the output comes up to the boot voltage of 1.1 v. the boot hold time is determined by the delay pin as it goes through a second cycle (td3). during td3, the processor vid pins settle to the required vid code. when td3 is over, the ADP3193 soft starts either up or down to the final vid voltage (td4). after td4 has been completed and the pwrgd masking time (equal to vid on-the-fly masking) is completed, a third ramp on the delay pin sets the pwrgd blanking (td5). td1 td3 td2 td5 50s td4 ss 5v supply vtt i/o (ADP3193 en) delay vcc_core vr ready (ADP3193 pwrgd) cpu vid inputs vid invalid vid valid v boot (1.1v) v boot (1.1v) uvlo threshold 0.85v v vid v vid 1v v delay(th) (1.7v) 06263-006 figure 7. system start-up sequence phase detection sequence during startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the pwm outputs. normally, the ADP3193 operates as a 3-phase pwm controller. connecting the pwm3 pin to vcc programs 2-phase operation. prior to soft start, while en is low, the pwm3 pin sinks approximately 100 a. an internal comparator checks the voltage on pwm3 vs. a threshold of 3 v. if the pin is tied to vcc, it is above the threshold. otherwise, an internal current sink pulls the pin to gnd, which is below the threshold. pwm1 and pwm2 are low during the phase detection interval that occurs during the first three clock cycles of td2. after this time, if pwm3 is not pulled to vcc, the 100 a current sink is removed, and it functions as normal pwm output. if pwm3 is pulled to vcc, the 100 a current source is removed, and it is put into a high impedance state. the pwm outputs are logic-level devices intended for driving external gate drivers such as the adp3120a. because each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one output can be on at the same time to allow overlapping phases.
ADP3193 rev. a | page 10 of 32 master clock frequency the clock frequency of the ADP3193 is set with an external resistor connected from the rt pin to ground. the frequency follows the graph in figure 6 . to determine the frequency per phase, the clock is divided by the number of phases in use. if all phases are in use, divide by 3. if pwm3 is tied to vcc, divide the master clock by 2 for the frequency of the remaining phases. output voltage differential sensing the ADP3193 combines differential sensing with a high accuracy vid dac and reference, and a low offset error ampli- fier. this maintains a worst-case specification of 7.7 mv differential sensing error over its full operating output voltage and temperature range. the output voltage is sensed between the fb pin and fbrtn pin. fb should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remote sense ground point. the internal vid dac and precision reference are referenced to fbrtn, which has a minimal current of 65 a to allow accurate remote sensing. the internal error amplifier compares the output of the dac to the fb pin to regulate the output voltage. output current sensing the ADP3193 provides a dedicated current-sense amplifier (csa) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection. sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side mosfet. this amplifier can be configured several ways, depending on the objectives of the system, as follows: ? output inductor dcr sensing without a thermistor for lowest cost. ? output inductor dcr sensing with a thermistor for improved accuracy with tracking of inductor temperature. ? sense resistors for highest accuracy measurements. the positive input of the csa is connected to the csref pin, which is connected to the output voltage. the inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input cssum. the feedback resistor between cscomp and cssum sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. the gain of the amplifier is programmable by adjusting the feedback resistor. the difference between csref and cscomp is also used as a differential input for the current limit comparator. to provide the best accuracy for sensing current, the csa is designed to have a low offset input voltage. in addition, the sensing gain is determined by external resistors to make it extremely accurate. current control mode and thermal balance the ADP3193 has individual inputs (sw1 to sw3) for each phase that are used to monitor the current in each phase. this information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. this current balance information is independent of the average output current information used for positioning as described in the output current sensing section. the magnitude of the internal ramp can be set to optimize the transient response of the system. it also monitors the supply voltage for feed-forward control for changes in the supply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. external resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase has better cooling and can support higher currents. resistor r sw1 through resistor r sw3 (see figure 10 ) can be used for adjusting thermal balance in this 3-phase example. it is best to have the ability to add these resistors during the initial design, therefore, ensure that placeholders are provided in the layout. to increase the current in any given phase, enlarge r sw for that phase (make r sw = 0 for the hottest phase and do not change it during balancing). increasing r sw to only 500 makes a substantial increase in phase current. increase each r sw value by small amounts to achieve balance, starting with the coolest phase first. voltage control mode a high gain, high bandwidth, voltage mode error amplifier is used for the voltage mode control loop. the control input voltage to the positive input is set via the vid logic according to the voltages listed in table 4 . this voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input (fb) is tied to the output sense location with resistor r b and is used for sensing and controlling the output voltage at this point. a current source (equal to iref) from the fb pin flowing through r b b b is used for setting the no load offset voltage from the vid voltage. th e no load voltage is negative
ADP3193 rev. a | page 11 of 32 with respect to the vid dac. the main loop compensation is incorporated into the feedback network between fb and comp. current reference the iref pin is used to set an internal current reference. this reference current sets i fb , i delay , i ss , and i limit . a resistor to ground programs the current based on the 1.5 v output. iref r iref v5.1 = typically, r iref is set to 100 k to program iref = 15 a. the following currents are then equal to i fb = iref = 15 a i delay = iref = 15 a i ss = iref = 15 a i limit = 2/3 (iref) = 10 a enhanced pwm mode enhanced pwm mode is intended to improve the transient response of the ADP3193 to a load step up. in previous generations of controllers, when a load step up occurred, the controller had to wait until the next turn-on of the pwm signal to respond to the load change. enhanced pwm mode allows the controller to immediately respond when a load step up occurs. this allows the phases to respond more quickly when a load increase takes place. delay timer the delay times for the start-up timing sequence are set with a capacitor from the delay pin to ground. in uvlo, or when en is logic low, the delay pin is held at ground. after the uvlo and en signals are asserted, the first delay time (td1 in figure 7 ) is initiated. a current flows out of the delay pin to charge c dly . this current is equal to iref, which is normally 15 a. a comparator monitors the delay voltage with a threshold of 1.7 v. the delay time is therefore set by the iref current charging a capacitor from 0 v to 1.7 v. this delay pin is used for multiple delay timings (td1, td3, and td5) during the start-up sequence. in addition, delay is used for timing the current-limit latch off, as explained in the current-limit, short-circuit, and latch-off protection section. soft start the soft start times for the output voltage are set with a capacitor from the ss pin to ground. after td1 and the phase detection cycle have been completed, the ss time (td2 in figure 7 ) starts. the ss pin is disconnected from gnd, and the capacitor is charged up to the 1.1 v boot voltage by the ss amplifier, which has an output current equal to iref (normally 15 a). the voltage at the fb pin follows the ramping voltage on the ss pin, limiting the inrush current during startup. the soft start time depends on the value of the boot voltage and c ss . once the ss voltage is within 100 mv of the boot voltage, the boot voltage delay time (td3 in figure 7 ) is started. the end of the boot voltage delay time signals the beginning of the second soft start time (td4 in figure 7 ). the ss voltage now changes from the boot voltage to the programmed vid dac voltage (either higher or lower) using the ss amplifier with the output current equal to iref. the voltage of the fb pin follows the ramping voltage of the ss pin, limiting the inrush current during the transition from the boot voltage to the final dac voltage. the second soft start time depends on the boot voltage, the programmed vid dac voltage, and c ss . if en is taken low or if vcc drops below uvlo, delay, and ss are reset to ground to be ready for another soft start cycle. figure 8 shows typical start-up waveforms for the ADP3193. ch1 1v ch2 1v ch4 10v ch3 1v m 1ms a ch1 700mv 1 2 3 4 t 40.4% 06263-007 figure 8. typical start-up waveforms (channel 1: csref, channel 2: delay, channel 3: ss, channel 4: phase 1 switch node) current-limit, short-circuit, and latch- off protection the ADP3193 compares a programmable current-limit set point to the voltage from the output of the current-sense amplifier. the level of current limit is set with the resistor from the ilimit pin to ground. during operation, the current from ilimit is equal to 2/3 of iref, giving 10 a normally. this current through the external resistor sets the ilimit voltage, which is internally scaled to give a current limit threshold of 82.6 mv/v. if the difference in voltage between csref and cscomp rises above the current-limit threshold, the internal current-limit amplifier controls the internal comp voltage to maintain the average output current at the limit. if the limit is reached and td5 in figure 7 has completed, a latch-off delay time starts, and the controller shuts down if the fault is not removed. the current-limit delay time shares the delay pin timing capacitor with the start-up sequence timing. however, during current limit, the delay pin current is
ADP3193 rev. a | page 12 of 32 reduced to iref/4. a comparator monitors the delay voltage and shuts off the controller when the voltage reaches 1.7 v. therefore, the current-limit latch-off delay time is set by the current of iref/4 charging the delay capacitor from 0 v to 1.7 v. this delay is four times longer than the delay time during the start-up sequence. the current-limit delay time starts only after the td5 is complete. if there is a current limit during startup, the ADP3193 goes through td1 to td5, and then starts the latch- off time. because the controller continues to cycle the phases during the latch-off delay time, the controller returns to normal operation and the delay capacitor is reset to gnd if the short is removed before the 1.7 v threshold is reached. the latch-off function can be reset by either removing and reapplying the supply voltage to the ADP3193, or by toggling the en pin low for a short time. to disable the short circuit latch-off function, an external resistor should be placed in parallel with c dly . this prevents the delay capacitor from charging up to the 1.7 v threshold. the addition of this resistor causes a slight increase in the delay times. during startup, when the output voltage is below 200 mv, a secondary current limit is active. this is necessary because the voltage swing of cscomp cannot go below ground. this secondary current limit controls the internal comp voltage to the pwm comparators to 1.5 v. this limits the voltage drop across the low-side mosfets through the current balance circuitry. an inherent per-phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. this limit is based on the maximum normal mode comp voltage. typical overcurrent latch-off waveforms are shown in figure 9 . ch1 1v ch2 1v ch4 10v ch3 2v m 2ms a ch1 680mv 3 2 1 4 t 61.8% 06263-008 figure 9. overcurrent latch-off waveforms (channel 1: csref, channel 2: delay, channel 3: comp, channel 4: phase 1 switch node) dynamic vid the ADP3193 has the ability to dynamically change the vid inputs while the controller is running. this allows the output voltage to change while the supply is running and supplying current to the load. this is commonly referred to as vid on- the-fly (otf). a vid otf can occur under light or heavy load conditions. the processor signals the controller by changing the vid inputs in multiple steps from the start code to the finish code. this change can be positive or negative. when a vid input changes state, the ADP3193 detects the change and ignores the dac inputs for a minimum of 400 ns. this time prevents a false code due to logic skew while the eight vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar blanking functions for a minimum of 100 s to prevent a false pwrgd or crowbar event. each vid change resets the internal timer. power-good monitoring the power-good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the nominal limits specified based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range, if the vid dac inputs are in no cpu mode, or if the en pin is pulled low. pwrgd is blanked during a vid otf event for a period of 200 s to prevent false signals during the time the output is changing. the pwrgd circuitry also incorporates an initial turn-on delay time (td5), based on the delay timer. prior to the ss voltage reaching the programmed vid dac voltage and the pwrgd masking-time finishing, the pwrgd pin is held low. once the ss pin is within 100 mv of the programmed dac voltage, the capacitor on the delay pin begins to charge. a comparator monitors the delay voltage and enables pwrgd when the voltage reaches 1.7 v. the pwrgd delay time is, therefore, set by a current of iref, charging a capacitor from 0 v to 1.7 v. output crowbar to protect the load and output components of the supply, the pwm outputs are driven low, which turns on the low-side mosfets when the output voltage exceeds the upper crowbar threshold. this crowbar action stops once the output voltage falls below the release threshold of approximately 300 mv. turning on the low-side mosfets pulls down the output as the reverse current builds up in the inductors. if the output overvoltage is due to a short in the high-side mosfet, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
ADP3193 rev. a | page 13 of 32 output enable and uvlo for the ADP3193 to begin switching, the input supply (vcc) to the controller must be higher than the uvlo threshold and the en pin must be higher than its 0.85 v threshold. this initiates a system start-up sequence. if either uvlo or en is less than their respective thresholds, the ADP3193 is disabled. this holds the pwm outputs at ground, shorts the delay capacitor to ground, and forces pwrgd and od signals low. in the application circuit (see figure 10 ), the od pin should be connected to the od inputs of the adp3120a drivers. grounding od disables the drivers such that both drvh and drvl are grounded. this feature is important in preventing the discharge of the output capacitors when the controller is shut off. if the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors.
ADP3193 rev. a | page 14 of 32 table 4.vr11 and vr10.x vid codes for the ADP3193 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 off 0 0 0 0 0 0 0 0 n/a off 0 0 0 0 0 0 0 1 n/a 1.60000 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1.59375 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1.58750 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1.58125 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1.57500 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1.56875 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0 1.56250 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1.55625 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1.55000 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 1.54375 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1.53750 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1.53125 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 1.52500 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 1.51875 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 1.51250 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1.50625 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1.50000 0 0 0 1 0 0 1 0 0 1 1 1 0 1 1 1.49375 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0 1.48750 0 0 0 1 0 1 0 0 0 1 1 1 1 0 1 1.48125 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1.47500 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1.46875 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1.46250 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1.45625 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1.45000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1.44375 0 0 0 1 1 0 1 1 1 0 0 0 0 1 0 1.43750 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 1.43125 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0 1.42500 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1.41875 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 1.41250 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1.40625 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1.40000 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1.39375 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 1.38750 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1.38125 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1.37500 0 0 1 0 0 1 1 0 1 0 0 1 1 1 1 1.36875 0 0 1 0 0 1 1 1 1 0 0 1 1 1 0 1.36250 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 1.35625 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 1.35000 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1.34375 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1.33750 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 1.33125 0 0 1 0 1 1 0 1 1 0 1 0 1 0 0 1.32500 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1.31875 0 0 1 0 1 1 1 1 1 0 1 0 1 1 0 1.31250 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1.30625 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1.30000 0 0 1 1 0 0 1 0 1 0 1 1 0 1 1 1.29375 0 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1.28750 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1.28125 0 0 1 1 0 1 0 1 1 0 1 1 1 0 0 1.27500 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1.26875 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1.26250 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1
ADP3193 rev. a | page 15 of 32 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 1.25625 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1.25000 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 1.24375 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 1.23750 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1.23125 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 1.22500 0 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1.21875 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1.21250 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 1.20625 0 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1.20000 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1.19375 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1.18750 0 1 0 0 0 1 0 0 1 1 0 1 1 0 1 1.18125 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 1.17500 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1.16875 0 1 0 0 0 1 1 1 1 1 0 1 1 1 0 1.16250 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1.15625 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1.15000 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1.14375 0 1 0 0 1 0 1 1 1 1 1 0 0 1 0 1.13750 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1.13125 0 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1.12500 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1.11875 0 1 0 0 1 1 1 1 1 1 1 0 1 1 0 1.11250 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1.10625 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 1.10000 0 1 0 1 0 0 1 0 1 1 1 1 0 1 1 1.09375 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0 off n/a 1 1 1 1 1 0 1 off n/a 1 1 1 1 1 0 0 off n/a 1 1 1 1 1 1 1 off n/a 1 1 1 1 1 1 0 1.08750 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1.08125 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1.07500 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1.06875 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1.06250 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1 1.05625 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 1.05000 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1.04375 0 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1.03750 0 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1.03125 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 1.02500 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1.01875 0 1 0 1 1 1 1 1 0 0 0 1 0 1 0 1.01250 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1.00625 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1.00000 0 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0.99375 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0.98750 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0.98125 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0.97500 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0.96875 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0.96250 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0.95625 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 0.95000 0 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0.94375 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0.93750 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0.93125 0 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0.92500 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1
ADP3193 rev. a | page 16 of 32 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 0.91875 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 0.91250 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 0.90625 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0.90000 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0.89375 0 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0.88750 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0.88125 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0.87500 0 1 1 1 0 1 1 0 0 1 0 0 0 1 1 0.86875 0 1 1 1 0 1 1 1 0 1 0 0 0 1 0 0.86250 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0.85625 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0 0.85000 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1 0.84375 0 1 1 1 1 0 1 1 0 1 0 0 1 1 0 0.83750 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0.83125 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0.82500 0 1 1 1 1 1 1 0 n/a 0.81875 0 1 1 1 1 1 1 1 n/a 0.81250 1 0 0 0 0 0 0 0 n/a 0.80625 1 0 0 0 0 0 0 1 n/a 0.80000 1 0 0 0 0 0 1 0 n/a 0.79375 1 0 0 0 0 0 1 1 n/a 0.78750 1 0 0 0 0 1 0 0 n/a 0.78125 1 0 0 0 0 1 0 1 n/a 0.77500 1 0 0 0 0 1 1 0 n/a 0.76875 1 0 0 0 0 1 1 1 n/a 0.76250 1 0 0 0 1 0 0 0 n/a 0.75625 1 0 0 0 1 0 0 1 n/a 0.75000 1 0 0 0 1 0 1 0 n/a 0.74375 1 0 0 0 1 0 1 1 n/a 0.73750 1 0 0 0 1 1 0 0 n/a 0.73125 1 0 0 0 1 1 0 1 n/a 0.72500 1 0 0 0 1 1 1 0 n/a 0.71875 1 0 0 0 1 1 1 1 n/a 0.71250 1 0 0 1 0 0 0 0 n/a 0.70625 1 0 0 1 0 0 0 1 n/a 0.70000 1 0 0 1 0 0 1 0 n/a 0.69375 1 0 0 1 0 0 1 1 n/a 0.68750 1 0 0 1 0 1 0 0 n/a 0.68125 1 0 0 1 0 1 0 1 n/a 0.67500 1 0 0 1 0 1 1 0 n/a 0.66875 1 0 0 1 0 1 1 1 n/a 0.66250 1 0 0 1 1 0 0 0 n/a 0.65625 1 0 0 1 1 0 0 1 n/a 0.65000 1 0 0 1 1 0 1 0 n/a 0.64375 1 0 0 1 1 0 1 1 n/a 0.63750 1 0 0 1 1 1 0 0 n/a 0.63125 1 0 0 1 1 1 0 1 n/a 0.62500 1 0 0 1 1 1 1 0 n/a 0.61875 1 0 0 1 1 1 1 1 n/a 0.61250 1 0 1 0 0 0 0 0 n / a 0.60625 1 0 1 0 0 0 0 1 n/a 0.60000 1 0 1 0 0 0 1 0 n/a 0.59375 1 0 1 0 0 0 1 1 n/a 0.58750 1 0 1 0 0 1 0 0 n/a 0.58125 1 0 1 0 0 1 0 1 n/a 0.57500 1 0 1 0 0 1 1 0 n/a 0.56875 1 0 1 0 0 1 1 1 n/a 0.56250 1 0 1 0 1 0 0 0 n/a
ADP3193 rev. a | page 17 of 32 vr11 dac codes: vidsel = high vr10.x dac codes: vidsel = low output vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vid4 vid3 vid2 vid1 vid0 vid5 vid6 0.55625 1 0 1 0 1 0 0 1 n/a 0.55000 1 0 1 0 1 0 1 0 n/a 0.54375 1 0 1 0 1 0 1 1 n/a 0.53750 1 0 1 0 1 1 0 0 n/a 0.53125 1 0 1 0 1 1 0 1 n/a 0.52500 1 0 1 0 1 1 1 0 n/a 0.51875 1 0 1 0 1 1 1 1 n/a 0.51250 1 0 1 1 0 0 0 0 n/a 0.50625 1 0 1 1 0 0 0 1 n/a 0.50000 1 0 1 1 0 0 1 0 n/a off 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ADP3193 rev. a | page 18 of 32 v in 12v v in rtn vtt i/o power good r lim 100k ? 1% from cpu r2 178k ? 1% q3 ntd110n02 q1 ntd40n03 q7 ntd110n02 q5 ntd40n03 q11 ntd110n02 q9 ntd40n03 q4 ntd110n02 c dly 18nf v cc(core) 0.5v to 1.6v 56a tdc, 65a pk v cc(core) rtn v cc(sense) v ss(sense) 560f/4v x 8 sanyo sepc series 5m ? each l2 320nh/1.4m ? l1 370nh 18a c ss 18nf c8 1n f c1 r t 169k ? 1% c15 10nf c25 c32 c14 1f d2, 1n4148 d3, 1n4148 d4, 1n4148 c11 10nf c10 1f c12 4.7f c16 4.7f u1 ADP3193 c19 10nf l4 320nh/1.4m ? c18 1f c4 1f c3 100f (optional) r a 22.1k ? c fb 15pf c a 220pf c b 560pf c cs1 1nf 5% npo c cs2 1nf 5% npo c2 2700f/16v/3.3a 2 sanyo mv-wx series 10f 26 mlcc in socket rth2 100k ? , 5% ntc c9 18nf r4 2.2 ? c13 18nf r5 2.2 ? c17 18nf r6 2.2 ? r b 1.21k ? r3 1 ? r cs1 35.7k ? r ph3 158k ? 1% r ph2 158k ? 1% r ph1 158k ? 1% q12 ntd110n02 q10 ntd40n03 q6 ntd40n03 q2 ntd40n03 c20 4.7f q8 ntd110n02 r sw1 * r sw2 * r sw3 * r cs2 88.7k ? 32 c5 1nf c7 1nf 10? ** 10? ** 10 ? ** l3 320nh/1.4m ? r iref 100k ? 12v 680? 680 ? 1k? 1f 12v vid7 vcc pwm1 pwm2 pwm3 sw1 sw2 sw3 vidsel vid0 vid1 vid2 vid3 vid4 vid5 vid6 en pwrgd fbrtn fb comp ss delay ilimit iref od gnd cscomp cssum csref rampadj rt 1 2 3 4 8 7 6 5 u2 adp3120a drvh sw pgnd drvl bst in vcc od 1 2 3 4 8 7 6 5 u3 adp3120a drvh sw pgnd drvl bst in vcc od 1 2 3 4 8 7 6 5 u4 adp3120a drvh sw pgnd drvl bst in vcc od + + + + + 1 *for a description of optional r sw resistors, see the theory of operation section. **connect near each inductor. 06263-009 figure 10. typical 3-phase application circuit
ADP3193 rev. a | page 19 of 32 application information the design parameters for a typical intel vrd 11 compliant cpu application are as follows: ? input voltage (v in ) = 12 v ? vid setting voltage (v vid ) = 1.400 v ? duty cycle (d) = 0.117 ? nominal output voltage at no load (v onl ) = 1.381 v ? nominal output voltage at 65 a load (v ofl ) = 1.316 v ? static output voltage drop based on a 1.0 m load line (r o ) from no load to full load (v d ) = v onl ? v ofl = 1.381 v ? 1.316 v = 65 mv ? maximum output current (i o ) = 65 a ? maximum output current step (i o ) = 50 a ? maximum output current slew rate (s r ) = 200 a/s ? number of phases (n) = 3 ? switching frequency per phase (f sw ) = 330 khz setting the clock frequency the ADP3193 uses a fixed frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses as well as the sizes of the inductors, the input capacitors, and output capacitors. with n = 3 for three phases, a clock frequency of 990 khz sets the switching frequency (f sw ) of each phase to 330 khz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. figure 6 shows that to achieve a 990 khz oscillator frequency, the correct value for r t is 169 k ( closest 1% resistor is 169 k). alternatively, the value for r t can be calculated using pf6 1 = sw t fn r (1) where 6 pf is the internal ic component values. for good initial accuracy and frequency stability, a 1% resistor is recommended. soft start delay time the value of c ss sets the soft start time. the ramp is generated with a 15 a internal current source. the value for c ss can be found using boot ss v td c 2 a15 = (2) where td2 is the desired soft start time and v boot is internally set to 1.1 v. assuming a desired td2 time of 1.4 ms, c ss is 19 nf. the closest standard value for c ss is 18 nf. although c ss also controls the time delay for td4 (determined by the final vid voltage), the minimum specification for td4 is 0 ns. this means that as long as the td2 time requirement is met, td4 is within the specification. current-limit latc h-off delay times the start-up and current-limit delay times are determined by the capacitor connected to the delay pin. the first step is to set c dly for the td1, td3, and td5 delay times (see figure 7 ). the delay ramp ( i delay ) is generated using a 15 a internal current source. the value for c dly can be approximated using )( )( thdelay delay dly v xtd ic = (3) where td(x) is the desired delay time for td1, td3, and td5. the delay threshold voltage ( v delay(th) ) is given as 1.7 v. in this example, 2 ms is chosen for all three delay times, which meets intel specifications. solving for c dly gives a value of 17.6 nf. the closest standard value for c dly is 18 nf. when the ADP3193 enters current limit, the internal current source changes from 15 a to 3.75 a. this makes the latch-off delay time 4 times longer than the start-up delay time. longer latch-off delay times can be achieved by placing a resistor in parallel with c dly . inductor selection the choice of inductance for the inductor determines the ripple current in the inductor. less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the mosfets. however, using smaller inductors allows the converter to meet a specified peak-to-peak transient deviation with less total output capacitance. conversely, a higher inductance means lower ripple current and reduced conduction losses, but more output capacitance is required to meet the same peak-to-peak transient deviation. in any multiphase converter, a practical value for the peak-to- peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. ( ) lf d v i sw vid r ? = 1 (4) equation 5 can be used to determine the minimum inductance based on a given output ripple voltage.
ADP3193 rev. a | page 20 of 32 () () ripple sw o vid vf dnrv l ? 1 (5) solving equation 5 for an output ripple voltage of 10 mv p-p yields () nh762 mv10khz330 350.1 m 1.0v41. = ? l if the resulting ripple voltage is less than what is designed for, the inductor can be made smaller until the ripple value is met. this allows optimal transient response and minimum output decoupling. the smallest possible inductor should be used to minimize the number of output capacitors. for this example, choosing a 320 nh inductor is a good starting point and gives a calculated ripple current of 11.7 a. the inductor should not saturate at the peak current of 27.6 a and should be able to handle the sum of the power dissipation caused by the average current of 21.7 a in the winding and core loss. another important factor in the inductor design is the dc resistance (dcr), which is used for measuring the phase currents. a large dcr can cause excessive power losses, though too small a value can lead to increased measurement error. a good rule is to have the dcr (r l ) be about 1 to 1? times the droop resistance (r o ). this example uses an inductor with a dcr of 1.4 m. designing an inductor once the inductance and dcr are known, the next step is to either design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. it is also important to have the inductance and dcr tolerance specified to control the accuracy of the system. reasonable tolerances most manufacturers can meet are 20% inductance and 7% dcr at room temperature. the first decision in designing the inductor is choosing the core material. several possibilities for providing low core loss at high frequencies include the powder cores (from micrometals, inc., for example, or kool-mu? from magnetics?) and the gapped soft ferrite cores (for example, 3f3 or 3f4 from philips). low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. the best choice for a core geometry is a closed-loop type such as a potentiometer core; pq, u, or e core; or toroid. a good compromise between price and performance is a core with a toroidal shape. many useful magnetics design references are available for quickly designing a power inductor, such as ? magnetic designer software from intusoft ? designing magnetic components for high frequency dc- dc converters , by william t. mclyman, k g magnetics, inc., isbn 1883107008 selecting a standard inductor the following power inductor manufacturers can provide design consultation and deliver power inductors optimized for high power applications upon request. ? coilcraft, inc. ? coiltronics ? sumida corporation current sense amplifier most designs require the regulator output voltage, measured at the cpu pins, to droop when the output current increases. the specified voltage drop corresponds to a dc output resistance (r o ), also referred to as a load line. the output current is measured by summing the voltage across each inductor and passing the signal through a low-pass filter. this summer filter is the cs amplifier configured with resistors r ph(x) (summers), and r cs and c cs (filter). the impedance gain of the regulator is set by the following equations, where r l is the dcr of the output inductors: () l xph cs o r r r r = (6) cs l cs rr l c = (7) the user has the flexibility to choose either r cs or r ph(x) . however, it is best to select r cs equal to 100 k, and then solve for r ph(x) by rearranging equation 6. here, r o = 1 m because this is equal to the design load line. () () k140k100 m 0.1 m4.1 == = xph cs o l x ph r r r r r next, use equation 7 to solve for c cs . nf82.2 k100m4.1 nh320 = = cs c it is best to have a dual location for c cs in the layout so that standard values can be used in parallel to get as close to the desired value. for best accuracy, c cs should be a 5% or 10%
ADP3193 rev. a | page 21 of 32 npo capacitor. this example uses a 5% combination for c cs of two 1 nf capacitors in parallel. recalculating r cs and r ph(x) using this capacitor combination yields 114 k and 160 k. the closest standard 1% value for r ph(x) is 158 k. inductor dcr temperature correction when the inductor dcr is used as the sense element and copper wire is used as the source of the dcr, the user needs to compensate for temperature changes of the inductors winding. fortunately, copper has a well known temperature coefficient (tc) of 0.39%/c. if r cs is designed to have an opposite and equal percentage change in resistance to that of the wire, it cancels the tempera- ture variation of the inductor dcr. due to the nonlinear nature of ntc thermistors, resistor r cs1 and resistor r cs2 are needed. see figure 11 to linearize the ntc and produce the desired temperature tracking. cssum 13 cscomp place as close as possible to nearest inductor or low-side mosfet 12 csref 11 ADP3193 c cs1 c cs2 r cs1 r th r cs2 keep this path as short as possible and well away from switch node lines to switch nodes to vout sense r ph1 r ph3 r ph2 06263-010 figure 11. temperature compensation circuit values the following procedure and equations yield values to use for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value. 1. select an ntc based on type and value. because the value is unknown, use a thermistor with a value close to r cs . the ntc should also have an initial tolerance of better than 5%. 2. based on the type of ntc, find its relative resistance value at two temperatures. the temperatures that work well are 50c and 90c. these resistance values are called a (r th(50c) )/r th(25c) ) and b (r th(90c) )/r th(25c) ). the relative value of the ntc is always 1 at 25c. 3. find the relative value of r cs required for each of these temperatures. this is based on the percentage change needed, which in this example is initially 0.39%/c. these temperatures are called r 1 (1/(1 + tc ( t 1 ? 25c))) and r 2 (1/(1 + tc ( t 2 ? 25c))), where tc = 0.0039 for copper, t 1 = 50c, and t 2 = 90c. from this, r 1 = 0.9112 and r 2 = 0.7978. 4. compute the relative values for r cs1 , r cs2 , and r th using ( ) () ( ) () () ( ) ????? ? + ?? ? = 1 1 1 1 (8) ( ) ? ? ? ? = 1 1 1 (9) cs1 cs2 th rr r 1 1 1 1 ? ? = (10) calculate r th = r th r cs , then select the closest value of thermistor available. in addition, compute a scaling factor (k ) based on the ratio of the ac tual thermistor value used relative to the computed one. () () = (11) 5. calculate values for r cs1 and r cs2 using equation 12 and 13. cs1 cs cs1 rkrr = (12) ( ) ( ) ( ) + ? = 1 (13) in this example, r cs is calculated to be 114 k. look for an available 100 k thermistor, 0603 size. one such thermistor is the vishay nths0603n01n1003jr ntc thermistor with a = 0.3602 and b = 0.09174. from these values, r cs1 = 0.3795, r cs2 = 0.7195, and r th = 1.075. solving for r th yields 122.55 k, so 100 k is chosen, making k = 0.816. next, find r cs1 and r cs2 to be 35.3 k and 87.9 k. finally, choose the closest 1% resistor values, which yields a choice of 35.7 k and 88.7 k. output offset the intel specification requires that at no load the nominal output voltage of the regulator is offset to a value lower than the nominal voltage corresponding to the vid code. the offset is set by a constant current source flowing out of the fb pin (i fb ) and flowing through r b . the value of r b b b can be found using equation 14 fb onl vid b i v v r ? = k27.1 a15 v381.1v4.1 = ? = (14) the closest standard 1% resistor value is 1.27 k. c out selection the required output decoupling for the regulator is typically recommended by intel for various processors and platforms. use some simple design guidelines to determine the require- ments. these guidelines are based on having both bulk capacitors and ceramic capacitors in the system.
ADP3193 rev. a | page 22 of 32 ed. the best ight after tual first, select the total amount of ceramic capacitance. this is based on the number and type of capacitor to be us location for ceramic capacitors is inside the socket, with from 12 to 18, 1206 size being the physical limit. other capacitors can be placed along the outer edge of the socket as well. to determine the minimum amount of ceramic capacitance required, start with a worst-case load step occurring r a switching cycle has stopped. the ceramic capacitance then delivers the charge to the load while the load is ramping up and until the vr has responded with the next switching cycle. equation 20 gives the designer a rough approximation for determining the minimum ceramic capacitance. due to the complexity of the pcb parasitics and bulk capacitors, the ac amount of ceramic capacitance required can vary. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? s o i d nfr minz c 2 11 2 1 (15) r swo the typical ceramic capacitors consist of mult 22 f capacitors. for this example, equation 15 yields 265 f, so considers the vid on-the- ximum load step (i o ) and a maximum ge iple 10 f or 26 10 f ceramic capacitors suffice. next, there is an upper limit imposed on the total amount of bulk capacitance (c x ) when the user fly voltage stepping of the output (voltage step v v in time t v with error of v err ). a lower limit is based on meeting the capacitance for load release for a given ma allowable overshoot. the total amount of load release volta is given as v o = i o r o + v rl , where v rl is the maximum allowable overshoot voltage. () ? ? ? ? ? ? ? ? ? o il ? ? ? ? ? ? ? ? ? ? ? ? ? ? + z vid o rl o minx c v i v rn c (16) (17) () maxx c z o v vid v vid v c lv t v ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 o 2 nkr v v rnk l ? ? ? ? ? ? ? ? 2 where ? ? ? ? ? ? ? ? ?= v err v v nk 1 . t he conditions o hese equations and transient response, the esr of the bulk capacitor bank (r x ) should be less rger um allowable load release o meet t f t than two times the droop resistance (r o ). if the c x(min) is la than c x(max) , the system cannot meet the vid on-the-fly speci- fication and can require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). this example uses 26, 10 f 1206 mlc capacitors ( c z = 260 f). the vid on-the-fly step change is 450 mv in 230 s with a settling error of 2.5 mv. the maxim overshoot for this example is 50 mv, therefore, solving for the bulk capacitance yields () mf64.1f260 v4.1 a50 mv50 m 0.13 a50nh320 ? ? ? ? ? ? ? ? ? minx c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + () () v4.1m0.12.53 mv450nh320 2 2 maxx c mf 42.7 f2601 nh320mv450 m01253v41s230 1 2 =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ... where k = 5.2. usin eight, 560 f al-poly capacitors with a typical esr of 6 m each yields c x = 4.48 mf with an r x = 0.75 m. ould be made to ensure that the esl of the g one last check sh bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using () ph347 3 4 m 1f260 x l 2 = (18) where q 2 is limited to 4 / 3 to ensure a critically damped system. in this example, l x is approximately 24 al-poly capacitors, which satisfies this limitation. if the l x ks ad 8 are satisfied. en tch and two low-side switches per n parameters for the power mosfets 2 2 o z x qrcl 0 ph for the eight, of the chosen bulk capacitor bank is too large, the number of ceramic c apacitors needs to be increased, or lower esl bul need to be used if there is excessive undershoot during a lo transient. for this multimode control tech nique, all ceramic designs can be used providing the conditions of equation 15 through equation 1 power mosfets for this example, the n-channel power mosfets have be selected for one high-side swi phase. the main selectio are v gs(th) , q g , c iss , c rss , and r ds(on) . the minimum gate drive voltage (the supply voltage to the adp3120a) dictates whether standard threshold or logic-level threshold mosfets must be
ADP3193 rev. a | page 23 of 32 ith ad between phases, thus, the vided s used. with v gate ~10 v, logic-level threshold mosfets (v gs(th) < 2.5 v) are recommended. the maximum output current (i o ) determines the r ds(on) requirement for the low-side (synchronous) mosfets. w the p3193, currents are balanced current in each low-side mosfet is the output current di by the total number of mosfets (n sf ). with conduction losse being dominant, the equation 19 shows the total power that is dissipated in each synchronous mosfet in terms of the ripple current per phase ( i r ) and average total output current ( i o ): () () sfds sf r sf o sf r n in n i dp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ?= 2 2 12 1 1 (19) knowing the maximum output current being designed f the maximum allowed power dissipation, the user can find the required r ds(on) for the mosfet. for d-pak mosfets up to s . ff e output impedance or t nd des or and an ambient temperature of 50c, a safe limit for p sf is 1 w to 1.5 w at 120c junction temperature. thus, for this example (56 a maximum), r ds(sf) (per mosfet) < 4.7 m. this r ds(sf) is also at a junction temperature of about 120c. as a result, users need to account for this when making this selection. thi example uses two lower-side mosfets at 4.8 m, each at 120 c another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous mosfets when the switch node goes high. in addition, the time to switch the synchronous mosfets o should not exceed the nonoverlap dead time of the mosfet driver (45 ns typical for the adp3120a). th of the driver is approximately 2 , and the typical mosfet input gate resistances are about 1 to 2 . therefore, a total gate capacitance of less than 6000 pf should be adhered to. because two mosfets are in parallel, the input capacitance f each synchronous mosfet should be limited to 6000 pf. the high-side (main) mosfet has to be able to handle two main power dissipation components: conduction and switching losses. the switching loss is related to the amount of time i takes for the main mosfet to turn on and off, and to the current and voltage that are being switched. basing the switching speed on the rise and fall time of the gate driver impedance a mosfet input capacitance, the following expression provi an approximate value for the switching loss per main mosfet, where n mf is the total number of main mosfets: () iss mf g m f occ sw mfs c n n r n i v f p = 2 (20) where r g is the total gate resistance (2 for the adp3120a and about 1 for typical high speed switching mosfets, making r g = 3 ), and c iss is the input capacitance of the main mosfet. adding more main mosfets ( n mf ) does not help the switching loss per mosfet because the additional gate capacitance slows switching. use lower gate capacitance devices to reduce switching loss. the conduction loss of the main mosfet is given by the following, where r ds(mf) is the on resistance of the mosfet: () () mf ds mf r mf o mfc r n in n i dp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = 2 2 12 1 (21) typically, for main mosfets, the highest speed (low c iss ) device is preferred, but these usually have higher on resistance. select a device that meets the total power dissipation (about 1.5 w for a single d-pak) when combining the switching and conduction losses. for this example, an ntd40n03l is selected as the main mosfet (three total; n mf = 3), with c iss = 584 pf (max) and r ds(mf) = 19 m (max at t j = 120c). an ntd110n02l is selected as the synchro- nous mosfet (three total; n sf = 3), with c iss = 2710 pf (max) and r ds(sf) = 4.8 m (max at t j = 120c). the synchronous mosfet c iss is less than 6000 pf, satisfying this requirement. solving for the power dissipation per mosfet at i o = 56 a and i r = 11.7 a yields 1.53 w for each synchronous mosfet and 1.06 w for each main mosfet. a guideline to follow is to limit the mosfet power dissipation to 1.5 w. the values calculated in equation 20 and equation 21 comply with this guideline. finally, consider the power dissipation in the driver for each phase. this is best expressed as q g for the mosfets and is given by equation 22, where q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet. () cc cc gsf sf gmf mf sw drv viqnqn n f p ? ? ? ? ? ? ? ? ++ = 2 (22) also shown is the standby dissipation factor (i cc v cc ) of the driver. for the adp3120a, the maximum dissipation should be less than 400 mw. in this example, with i cc = 7 ma, q gmf = 5.8 nc, and q gsf = 48 nc, there is 191 mw in each driver, which is below the 400 mw dissipation limit. see the adp3120a data sheet for more details.
ADP3193 rev. a | page 24 of 32 ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. equation 23 is used for determining the optimum value. k 178 pf5m8.453 nh3200.2 3 = = = r r ds d r r r cra la r (23) where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low-side mosfet on resistance. c r is the internal ramp capacitor value. the internal ramp voltage magnitude can be calculated by using () () vm842 khz330pf5 ? k178 v41.170.110.2 1 = ? = ? = r swrr vid r r v fcr vda v (24) the size of the internal ramp can be made larger or smaller. if it is made larger, stability and noise rejection improves, but transient degrades. likewise, if the ramp is made smaller, transient response improves at the sacrifice of noise rejection and stability. the factor of 3 in the denominator of equation 23 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance. comp pin ramp a ramp signal on the comp pin is due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input: () ? ? ? ? ? ? ? ? ? ? = o x sw r rt rcfn dn v v 12 1 (25) in this example, the overall ramp signal is 1.19 v. however, if the ramp size is smaller than 0.5 v, increase the ramp size to be at least 0.5 v by decreasing the ramp resistor for noise immunity. current-limit setpoint to select the current-limit setpoint, first find the resistor value for r lim . the current-limit threshold for the ADP3193 is set with a constant current source flowing out of the ilimit pin, which sets up a voltage (v lim ) across r lim with a gain of 82.6 mv/v (a lim ). thus, increasing r lim now increases the current limit. r lim can be found using ref csa lim ilimit lim cl lim r ri ia v r = = mv6.82 (26) here, i lim is the peak average current limit for the supply output. the peak average current is the dc current limit plus the output ripple current. in this example, choosing a dc current limit of 88.3 a and having a ripple current of 11.7 a gives an i lim of 100 a. this results in an r lim = 121 k, for which 121 k is chosen as the nearest 1% value. the per-phase initial duty cycle limit and peak current during a load step are determined by () rt bias max comp max v v v dd ? = (27) ( ) l vv f d i vid in sw max phmax ? ? (28) for the ADP3193, the maximum comp voltage ( v comp(max) ) is 3.4 v and the comp pin bias voltage ( v bias ) is 1.1 v. in this example, the maximum duty cycle is 0.23. because this is small due to the v rt being much larger than 0.5 v, reduce the ramp resistor to get closer to 0.5 v v rt and obtain a larger duty cycle. choosing a ramp resistor of 267 k gives us a v rt of 0.79 v and a d max of 0.34. the peak current is then 34 a. the limit of the peak per-phase current described earlier during the secondary current limit is determined by () () max ds d bias clamped comp phlim ra v v i ? ? (29) for the ADP3193, the current balancing amplifier gain (a d ) is 5 and the clamped comp pin voltage is 2 v. using an r ds(max) of 5.6 m (low-side on resistance at 150c) results in a per-phase peak current limit of 36 a. this current level can be reached only with an absolute short at the output, and the current-limit latch-off function shuts down the regulator before overheating can occur. feedback loop comp ensation design optimized compensation of the ADP3193 allows the best possible response of the regulator output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion to the load current at any load current slew rate. this ensures optimal positioning and minimizes the output decoupling.
ADP3193 rev. a | page 25 of 32 because of the multimode feedback structure of the ADP3193, the feedback compensation must be set to make the converter output impedance work in parallel with the output decoupling to make the load look entirely resistive. compensation is needed for several poles and zeros created by the output inductor and the decoupling capacitors (output filter). a type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. equation 30 to equation 34 are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning the ADP3193 section). first, compute the time constants for all the poles and zeros in the system using equation 35 to equation 39. ( ) vid o x rt vid rt l ds d o e vrcn vdnl v vr rarnr ? + ++= 12 ( ) ? m3.45 v41. ? m1mf48.43 v790.350.1nh3202 v41. v790. ? m1.4 ? m8.45 ? m13 = ? + ++= e r (30) () () s47.2 m750. m0.5m1 m1 ph347 m0.5m1mf48.4 ' ' = ? +?= ? +?= x o o x o x a r rr r l rrct (31) ( ) ( ) ns0112mf48.4m1m0.5m750. ' = ?+=?+= x o xb crrrt (32) s53.3 m3.45v41. khz3302 m8.45 nh320v790. 2 = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? = evid sw ds d rt c rv f ra lv t (33) () ( ) () ns466 m1f026m0.5m1mf48.4 m1f026mf48.4 ' 2 2 = +? = +? = o z o x o z x d rcrrc rcc t (34) where: r ' is the pcb resistance from the bulk capacitors to the ceramics. r ds is the total low-side mosfet on resistance per phase. in this example, a d is 5, v rt equals 0.79 v, r ' is approximately 0.5 m (assuming a 4-layer, 1 ounce motherboard), and l x is 347 ph for the 8 al-poly capacitors.
ADP3193 rev. a | page 26 of 32 the compensation values can then be solved using pf128 k271.m3.45 s47.2m13 = = = be ao a rr trn c (35) k5.27 pf128 s53.3 === a c a c t r (36) pf882 k271. ns1120 === b b b r t c (37) pf9.16 k5.27 ns466 === a d fb r t c (38) these are the starting values prior to tuning the design that account for layout and other parasitic effects (see the tun ing t he ADP3193 section). the final values selected after tuning are c a = 220 pf r a = 22.1 k c b = 560 pf b c fb = 15 pf figure 12 and figure 13 show the typical transient response using these compensation values. 20mv/div 2s/div 06263-015 figure 12. typical transient respon se for design example load step 20mv/div 2s/div 06263-016 figure 13. typical transient response for design example load release c n selecton and nput current didt reducton in continuous inductor current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude of one-nth the maximum output current. to prevent large voltage transients, a low esr input capacitor, sized for the maximum rms current, must be used. the maximum rms capacitor current is given by a3.011 170.13 1 a65117.0 1 1 =? = ? = crms o crms i dn idi (39) the capacitor manufacturers ripple-current ratings are often based on only 2000 hours of life. as a result, it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors can be placed in parallel to meet size or height requirements in the design. in this example, the input capacitor bank is formed by two 2700 f, 16 v aluminum electrolytic capacitors and eight 4.7 f ceramic capacitors. to reduce the input current di/dt to a level below the recom- mended maximum of 0.1 a/s, an additional small inductor (l > 370 nh at 18 a) should be inserted between the converter and the supply bus. this inductor also acts as a filter between the converter and the primary power source. shunt resistor design the ADP3193 uses a shunt to generate 5 v from the 12 v supply range. a trade-off can be made between the power dissipated in the shunt resistor and the uvlo threshold. figure 13 shows the typical resistor value needed to realize certain uvlo voltages. it also gives the maximum power dissipated in the shunt resistor for these uvlo voltages. 550 150 7.0 11.0 v in (uvlo) r shunt ( ? ) p shunt (w) 500 450 400 350 300 250 200 0.50 0.10 0.45 0.40 0.35 0.30 0.25 0.20 0.15 7.5 8.0 8.5 9.0 9.5 10.0 10.5 r shunt p shunt 06263-018 figure 14. typical shunt resistor value and power dissipation for different uvlo voltage
ADP3193 rev. a | page 27 of 32 the maximum power dissipated is calculated using equation 40. ( ) shunt mincc maxin max r v v p 2 )()( ? = (40) and eq where: v in(max) is the maximum voltage from the 12 v input supply (if the 12 v input supply is 12 v 5%, v in(max) = 12.6 v; if the 12 v input supply is 12 v 10%, v in(max) = 13.2 v). v cc(min) is the minimum v cc voltage of the adp3192. this is specified as 4.75 v. r shunt is the shunt resistor value. the cecc standard specification for power rating in surface mount resistors is: 0603 = 0.1 w, 0805 = 0.125 w, 1206 = 0.25 w. tuning the ADP3193 1. build a circuit based on the compensation values computed from the design spreadsheet. 2. hook up the dc load to the circuit, turn it on, and verify its operation. also, check for jitter at no load and full load. dc load line setting 3. measure the output voltage at no load (v nl ). verify that it is within tolerance. 4. measure the output voltage at full load cold ( v flcold ). let the board sit for ~10 minutes at full load, and then measure the output ( v flhot ). if there is a change of more than a few mv, adju st r cs1 and r cs2 using equation 41 uation 47. () () flhot nl flcold nl oldcs2 newcs2 vv v v r r ? ? = (41) 5. ot voltage 6. n average to get the overall load line e (r 7. .05 m, use equation 42 to adjust the r ph values. repeat step 4 until the cold and h measurements remain the same. measure the output voltage from no load to full load using 5 a steps. compute the load line slope for each change, and the slop omeas ). if r omeas is off from r o by more than 0 () () o omeas oldph newph r r r r = (42) 8. check the load line. repeat 9. r cs1 , r cs2 , or r th for the remainder of the 10. with a scope, and make sure it is within specifications. repeat step 6 and step 7 to adjustments if necessary. when the dc load line adjustment is complete, do not change r ph , procedure. measure the output ripple at no load and full load () () ( ) () ( ) () () () () ( ) () () c25 c25 c25 c25 1 1 ? ? ? + + = th th oldcs1 newcs2 oldcs1 th oldcs1 th oldcs1 newcs1 r rr rr rr r r r (43)
ADP3193 rev. a | page 28 of 32 ac load line setting 11. remove the dc load from the circuit and hook up the dynamic load. 12. hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. set the dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 14. measure the output waveform (use dc offset on scope to see the waveform). try to use a vertical scale of 100 mv/div or finer. this waveform should look similar to figure 15 . v dcdrp v acdrp 0 6263-012 figure 15. ac load line waveform 15. use the horizontal cursors to measure v acdrp and v dcdrp as shown in figure 15 . do not measure the undershoot or overshoot that happens immediately after this step. 16. if v acdrp and v dcdrp are different by more than a few millivolts, use equation 44 to adjust c cs. users may need to parallel different values to get the right one because limited standard capacitor values are available. it is a good idea to have locations for two capacitors in the layout for this. () () = (44) 17. repeat step 11 to step 13 and repeat the adjustments, if necessary. once complete, do not change c cs for the remainder of the procedure. set the dynamic load step to maximum step size. do not use a step size larger than needed. verify that the output waveform is square, which means that v acdrp and v dcdrp are equal. initial transient setting 18. with the dynamic load still set at the maximum step size, expand the scope time scale to either 2 s/div or 5 s/div. the waveform can have two overshoots and one minor undershoot (see figure 16 ). here, v droop is the final desired value. v droop v tran2 v tran1 0 6263-013 figure 16. transient setting waveform 19. if both overshoots are larger than desired, try adjusting them by using the following suggestions: ? make the ramp resistor larger by 25% (r ramp ). ? for v tran1 , increase c b or increase the switching frequency. b ? for v tran2 , increase r a and decrease c a by 25%. if these adjustments do not change the response, the design is limited by the output decoupling. check the output response every time a change is made, and check the switch- ing nodes to ensure that the response is still stable. 20. for load release (see figure 17 ), if v tranrel is larger than the allowed overshoot, there is not enough output capacitance. either more capacitance is needed, or the inductor values need to be made smaller. when changing inductors, start the design again using a spreadsheet and this tuning procedure. v droop v tranrel 0 6263-014 figure 17. transient setting waveform because the ADP3193 turns off all of the phases (switches inductors to ground), no ripple voltage is present during load release. therefore, the user does not have to add headroom for
ADP3193 rev. a | page 29 of 32 ripple, which allows load release v tranrel to be larger than v tran1 by the amount of ripple, and still meet specifications. if v tran1 and v tranrel are less than the desired final droop, this implies that capacitors can be removed. when removing capaci- tors, also check the output ripple voltage to make sure it is still within specifications. layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for good results, a pcb with at least four layers is recommended. this provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. whenever high currents must be routed between pcb layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the ADP3193) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. an analog ground plane should be used around and under the ADP3193 as a reference for the components associated with the controller. this plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. the components around the ADP3193 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb pin and cssum pin. the output capacitors should be connected as close as possible to the load (or connector), for example, a microproc- essor core, that receives the power. if the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop (described in the power circuitry recommendations section). power circuitry recommendations the switching power path should be routed on the pcb to encompass the shortest possible length to minimize radiated switching noise energy (emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system and noise-related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. when a power dissipating component, for example, a power mosfet, is soldered to a pcb, it is recommended to liberally use the vias, both directly on the mounting pad and immediately surrounding it. two important reasons for this are improved current rating through the vias and improved thermal perform- ance from vias extended to the opposite side of the pcb, where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heatsink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation in the air around the board. to further improve thermal performance, use the largest possible pad area. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. signal circuitry recommendations the output voltage is sensed and regulated between the fb pin and the fbrtn pin, which connect to the signal ground at the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be small. thus, the fb trace and fbrtn trace should be routed adjacent to each other on top of the power ground plane back to the controller. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be connected to the output voltage at the nearest inductor to the controller.
ADP3193 rev. a | page 30 of 32 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 18. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity ADP3193jcpz-rl 1 0c to 85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 2,500 1 z = pb-free part.
ADP3193 rev. a | page 31 of 32 notes
ADP3193 rev. a | page 32 of 32 t notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06263-0-8/06(a) ttt

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